SN74HC164
- Wide Operating Voltage Range of 2 V to 6 V
- Outputs Can Drive Up to 10 LSTTL Loads
- Low Power Consumption, 80-µA Maximum ICC
- Typical tpd = 20 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1-µA Maximum
- AND-Gated (Enable/Disable) Serial Inputs
- Fully Buffered Clock and Serial Inputs
- Direct Clear
- On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include
Testing of All Parameters.
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
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技术文档
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SNx4HC164 8-Bit Parallel-Out Serial Shift Registers 数据表 (Rev. G) | PDF | HTML | 2014-2-3 | ||
| 应用简报 | TI 逻辑系列的内插规格值 | PDF | HTML | PDF | HTML | 2026-4-17 | ||
| 应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022-12-15 | |||
| 技术文章 | How to create a dynamic power solution for stepper motors, relays and LEDs | PDF | HTML | 2016-11-1 | |||
| 应用手册 | HCMOS Design Considerations (Rev. A) | 2002-9-9 |
设计与开发
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评估板
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| PDIP (N) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |