主页 逻辑和电压转换 触发器、锁存器和寄存器 移位寄存器
主页
逻辑和电压转换
触发器、锁存器和寄存器
移位寄存器

SN74F299

正在供货

通用移位/存储寄存器

立即订购
数据表

SN74F299

正在供货
数据表 立即订购

产品详情

Configuration Universal Bits (#) 8 Technology family F Input type Bipolar Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 24 IOH (max) (mA) -3 Supply current (max) (µA) 95000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 8 Technology family F Input type Bipolar Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 24 IOH (max) (mA) -3 Supply current (max) (µA) 95000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operates With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operates With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.
filter 查找其他 移位寄存器
下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 2
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN54F299, SN74F299 数据表 (Rev. B) 2004-4-16
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
支持的产品和硬件
有库存
限制：
??asset.out-of-stock-ti_zh_CN??
无货
封装 引脚 CAD 符号、封装和 3D 模型
SOIC (DW) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

可获得 TI 工程师技术支持的 TI E2E™ 论坛

查看全部论坛主题 查看英文版全部论坛主题

所有内容均由 TI 和社区贡献者按“原样”提供，并不构成 TI 规范。请参阅使用条款。

如果您对质量、包装或订购 TI 产品有疑问，请参阅 TI 支持。​​​​​​​​​​​​​​

视频