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JK 触发器

SN74F109

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具有清零和预设功能的双通道 J-K 正边沿触发器

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SN74F109

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产品详情

Number of channels 2 Technology family F Input type TTL Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 19000 IOL (max) (mA) 20 IOH (max) (mA) -1 Features Clear, Positive edge triggered, Preset, Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Technology family F Input type TTL Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 19000 IOL (max) (mA) 20 IOH (max) (mA) -1 Features Clear, Positive edge triggered, Preset, Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.
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SN74HC109 正在供货 具有清零和预设功能的双通道 J-K 正边沿触发器 Voltage range 2V to 6V, average propagation delay 20ns, average drive strength 8mA

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Dual J-K Positive-Edge-Triggered Flip-Flops w/Clear And Preset 数据表 (Rev. A) 1993-10-1

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