SN74CBTLV3384

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具有 2 个控制输入的 3.3V、1:1 (SPST)、10 通道通用 FET 总线开关

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数据表

document-pdfAcrobat SN74CBTLV3384 数据表 (Rev. G) (英语)

SN74CBTLV3384

正在供货

数据表

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产品详情

Protocols

Analog

Configuration

1:1 SPST

Number of channels

10

Bandwidth (MHz)

200

Ron (typ) (mΩ)

5000

Input/output voltage (min) (V)

0

Input/output voltage (max) (V)

3.6

Operating temperature range (°C)

-40 to 85

Input/output continuous current (max) (mA)

128

COFF (typ) (pF)

10

OFF-state leakage current (max) (µA)

1

Ron (max) (mΩ)

40000

VIH (min) (V)

2

VIL (max) (V)

0.8

Rating

Catalog

Protocols

Analog

Configuration

1:1 SPST

Number of channels

10

Bandwidth (MHz)

200

Ron (typ) (mΩ)

5000

Input/output voltage (min) (V)

0

Input/output voltage (max) (V)

3.6

Operating temperature range (°C)

-40 to 85

Input/output continuous current (max) (mA)

128

COFF (typ) (pF)

10

OFF-state leakage current (max) (µA)

1

Ron (max) (mΩ)

40000

VIH (min) (V)

2

VIL (max) (V)

0.8

Rating

Catalog

SOIC (DW)

24

159.65 mm² (15.5 mm × 10.3 mm)

SSOP (DBQ)

24

51.9 mm² (8.65 mm × 6 mm)

TVSOP (DGV)

24

32 mm² (5 mm × 6.4 mm)

TSSOP (PW)

24

49.92 mm² (7.8 mm × 6.4 mm)

5- Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

5- Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

The SN74CBTLV3384 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as dual 5-bit bus switches with separate output-enable (OE\) inputs. It can be used as two 5-bit bus switches or one 10-bit bus switch. When OE\ is low, the associated 5-bit bus switch is on and A port is connected to B port. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3384 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as dual 5-bit bus switches with separate output-enable (OE\) inputs. It can be used as two 5-bit bus switches or one 10-bit bus switch. When OE\ is low, the associated 5-bit bus switch is on and A port is connected to B port. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	SN74CBTLV3384 数据表 (Rev. G)				2004-6-15
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