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SN74CBTH16211

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具有总线保持功能的 5V、1:1 (SPST)、24 通道 FET 总线开关

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SN74CBTH16211

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产品详情

Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 Ron (max) (mΩ) 20000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 Ron (max) (mΩ) 20000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Bus Hold on Data Inputs/Outputs Eliminates the Need for External Pullup/Pulldown Resistors
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Bus Hold on Data Inputs/Outputs Eliminates the Need for External Pullup/Pulldown Resistors

The SN74CBTH16211 provides 24 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as dual 12-bit bus switches with separate output-enable (OE\) inputs. It can be used as two 12-bit bus switches or one 24-bit bus switch. When OE\ is low, the associated 12-bit bus switch is on, and the A port is connected to the B port. When OE\ is high, the switch is open, and a high-impedance state exists between the two ports.

Active bus-hold circuitry is provided to hold unused or floating A and B ports at a valid logic level.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTH16211 provides 24 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as dual 12-bit bus switches with separate output-enable (OE\) inputs. It can be used as two 12-bit bus switches or one 24-bit bus switch. When OE\ is low, the associated 12-bit bus switch is on, and the A port is connected to the B port. When OE\ is high, the switch is open, and a high-impedance state exists between the two ports.

Active bus-hold circuitry is provided to hold unused or floating A and B ports at a valid logic level.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 24-Bit FET Bus Switch With Bus Hold 数据表 (Rev. C) 2001-11-13
应用手册 选择正确的德州仪器 (TI) 信号开关 (Rev. E) PDF | HTML 英语版 (Rev.E) PDF | HTML 2022-8-5
应用手册 多路复用器和信号开关词汇表 (Rev. B) 英语版 (Rev.B) PDF | HTML 2022-3-11

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封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 56 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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