SN74CBT3384C

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具有 –2V 下冲保护的 3.3V、1:1 (SPST)、10 通道通用 FET 总线开关

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数据表

document-pdfAcrobat SN74CBT3384C 数据表 (Rev. A) (英语)

SN74CBT3384C

正在供货

数据表

立即订购

产品详情

Protocols

Analog

Configuration

1:1 SPST

Number of channels

10

Bandwidth (MHz)

200

Ron (typ) (mΩ)

3000

Input/output voltage (min) (V)

0

Input/output voltage (max) (V)

5.5

Operating temperature range (°C)

-40 to 85

ESD CDM (kV)

1

Input/output continuous current (max) (mA)

128

COFF (typ) (pF)

5

CON (typ) (pF)

12.5

OFF-state leakage current (max) (µA)

10

Ron (max) (mΩ)

12000

VIH (min) (V)

2

VIL (max) (V)

0.8

Rating

Catalog

Protocols

Analog

Configuration

1:1 SPST

Number of channels

10

Bandwidth (MHz)

200

Ron (typ) (mΩ)

3000

Input/output voltage (min) (V)

0

Input/output voltage (max) (V)

5.5

Operating temperature range (°C)

-40 to 85

ESD CDM (kV)

1

Input/output continuous current (max) (mA)

128

COFF (typ) (pF)

5

CON (typ) (pF)

12.5

OFF-state leakage current (max) (µA)

10

Ron (max) (mΩ)

12000

VIH (min) (V)

2

VIL (max) (V)

0.8

Rating

Catalog

SOIC (DW)

24

159.65 mm² (15.5 mm × 10.3 mm)

SSOP (DBQ)

24

51.9 mm² (8.65 mm × 6 mm)

TSSOP (PW)

24

49.92 mm² (7.8 mm × 6.4 mm)

TVSOP (DGV)

24

32 mm² (5 mm × 6.4 mm)

Undershoot Protection for Off-Isolation on A and B Ports Up to –2 V
Bidirectional Data Flow, With Near-Zero Propagation Delay
Low ON-State Resistance (r_on) Characteristics (r_on = 3 Typical)
Low Input/Output Capacitance Minimizes Loading and Signal Distortion (C_io(OFF) = 5 pF Typical)
Data and Control Inputs Provide Undershoot Clamp Diodes
Low Power Consumption (I_CC = 3 µA Max)
V_CC Operating Range From 4 V to 5.5 V
Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog Applications: PCI Interface, USB Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

Undershoot Protection for Off-Isolation on A and B Ports Up to –2 V
Bidirectional Data Flow, With Near-Zero Propagation Delay
Low ON-State Resistance (r_on) Characteristics (r_on = 3 Typical)
Low Input/Output Capacitance Minimizes Loading and Signal Distortion (C_io(OFF) = 5 pF Typical)
Data and Control Inputs Provide Undershoot Clamp Diodes
Low Power Consumption (I_CC = 3 µA Max)
V_CC Operating Range From 4 V to 5.5 V
Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog Applications: PCI Interface, USB Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

The SN74CBT3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r_on), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3384C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3384C is organized as two 5-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE\ is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 5-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r_on), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3384C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3384C is organized as two 5-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE\ is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 5-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	SN74CBT3384C 数据表 (Rev. A)				2003-10-15
	应用手册	选择正确的德州仪器 (TI) 信号开关 (Rev. E)	PDF \| HTML	英语版 (Rev.E)	PDF \| HTML	2022-8-5
	应用手册	多路复用器和信号开关词汇表 (Rev. B)		英语版 (Rev.B)	PDF \| HTML	2022-3-11
	应用简报	利用关断保护信号开关消除电源时序 (Rev. C)		英语版 (Rev.C)	PDF \| HTML	2021-10-21