产品详情

Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 100 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 13 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 9500 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 100 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 13 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 9500 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
TVSOP (DGV) 56 72.32 mm² (11.3 mm × 6.4 mm) TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm) SSOP (DL) 56 190.647 mm² (18.42 mm × 10.35 mm)
  • Member of the Texas Instruments Widebus Family
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on
    All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level
      Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output
      Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up
    or Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes
    Loading (Cio(OFF) = 5 pF Typ)
  • Data and Control Inputs Provide
    Undershoot Clamp Diodes
  • Low Power Consumption
    (ICC = 70 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL
    or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level
    Translation, PCI Interface, Bus Isolation
  • Ideal for Low-Power Portable Equipment

  • Member of the Texas Instruments Widebus Family
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on
    All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level
      Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output
      Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up
    or Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes
    Loading (Cio(OFF) = 5 pF Typ)
  • Data and Control Inputs Provide
    Undershoot Clamp Diodes
  • Low Power Consumption
    (ICC = 70 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL
    or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level
    Translation, PCI Interface, Bus Isolation
  • Ideal for Low-Power Portable Equipment

The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground.

The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground.

The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74CB3T16211 数据表 (Rev. C) 2012-8-17
应用手册 选择正确的德州仪器 (TI) 信号开关 (Rev. E) PDF | HTML 英语版 (Rev.E) PDF | HTML 2022-8-5
应用手册 多路复用器和信号开关词汇表 (Rev. B) 英语版 (Rev.B) PDF | HTML 2022-3-11
应用简报 利用关断保护信号开关消除电源时序 (Rev. C) 英语版 (Rev.C) PDF | HTML 2021-10-21

设计与开发

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仿真模型

HSPICE Model for SN74CB3T16211

SCDJ036.ZIP (118 KB) - HSpice 模型
支持的产品和硬件
仿真模型

SN74CB3T16211 IBIS Model

SCDM096.ZIP (28 KB) - IBIS 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
TVSOP (DGV) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
SSOP (DL) 56 Ultra Librarian

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