主页 逻辑和电压转换 触发器、锁存器和寄存器 D 型触发器
主页
逻辑和电压转换
触发器、锁存器和寄存器
D 型触发器

SN74AVC16722

正在供货

具有三态输出的 22 位触发器

立即订购
数据表

SN74AVC16722

正在供货
数据表 立即订购

产品详情

Number of channels 22 Technology family AVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 175 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 22 Technology family AVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 175 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
TSSOP (DGG) 64 137.7 mm² (17 mm × 8.1 mm)
  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class I
  • Packaged in Thin Shrink Small-Outline Package

    DOC, EPIC, and Widebus are trademarks of Texas Instruments.
  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class I
  • Packaged in Thin Shrink Small-Outline Package

    DOC, EPIC, and Widebus are trademarks of Texas Instruments.

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM ) Circuitry Technology and Applications, literature number SCEA009.

This 22-bit flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN\) input. On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN\ is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE\) input places the 22 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16722 is characterized for operation from -40°C to 85°C.

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM ) Circuitry Technology and Applications, literature number SCEA009.

This 22-bit flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN\) input. On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN\ is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE\) input places the 22 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16722 is characterized for operation from -40°C to 85°C.
filter 查找其他 D 型触发器
下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 2
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 22-Bit Flip-Flop With 3-State Outputs 数据表 (Rev. H) 2000-6-29
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 64 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

可获得 TI 工程师技术支持的 TI E2E™ 论坛

查看全部论坛主题 查看英文版全部论坛主题

所有内容均由 TI 和社区贡献者按“原样”提供，并不构成 TI 规范。请参阅使用条款。

如果您对质量、包装或订购 TI 产品有疑问，请参阅 TI 支持。​​​​​​​​​​​​​​

视频