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D 型锁存器

SN74AS373

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具有三态输出的八通道 D 类透明锁存器

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数据表

SN74AS373

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数据表 立即订购

产品详情

Number of channels 8 Technology family AS Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 125 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 100000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 8 Technology family AS Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 125 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 100000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Eight Latches in a Single Package
  • 3-State Bus-Driving True Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • pnp Inputs Reduce dc Loading on Data Lines
  • Eight Latches in a Single Package
  • 3-State Bus-Driving True Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • pnp Inputs Reduce dc Loading on Data Lines

These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Octal Transparent D-Type Latches With 3-State Outputs 数据表 (Rev. C) 2002-3-6

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