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SN74ALVCH16863

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具有三态输出的 18 位收发器

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SN74ALVCH16863

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产品详情

Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type LVTTL Output type LVTTL Features Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type LVTTL Output type LVTTL Features Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm)
  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

This 18-bit bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16863 is an 18-bit noninverting transceiver designed for synchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The SN74ALVCH16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16863 is characterized for operation from -40°C to 85°C.

This 18-bit bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16863 is an 18-bit noninverting transceiver designed for synchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The SN74ALVCH16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16863 is characterized for operation from -40°C to 85°C.

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SN74ABT16863 正在供货 具有三态输出的 18 位总线收发器 Voltage range 4.5V to 5.5V, average propagation delay 4.6ns, average drive strength 64mA

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 18-Bit Transceiver With 3-State Outputs 数据表 (Rev. B) 1999-2-11
应用手册 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018-9-17

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封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 56 Ultra Librarian
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