SN74ALVCH16841
- Member of the Texas Instruments Widebus™ Family
- EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
Widebus, EPIC are trademarks of Texas Instruments.
This 20-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16841 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers.
The SN74ALVCH16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OE\ does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16841 is characterized for operation from -40°C to 85°C.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SN74ALVCH16841 数据表 (Rev. E) | 2004-8-20 | |||
| 应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022-12-15 | |||
| 应用手册 | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 2018-9-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SSOP (DL) | 56 | Ultra Librarian |
| TSSOP (DGG) | 56 | Ultra Librarian |