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SN74ALVCH16271

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具有三态输出的 12 位至 24 位多路复用总线交换器

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SN74ALVCH16271

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产品详情

Number of channels 24 IOL (max) (mA) 24 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 24 IOL (max) (mA) 24 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm)
  • Member of Texas Instruments Widebus™Family
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.
  • Member of Texas Instruments Widebus™Family
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

This 12-bit to 24-bit bus exchanger is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors.

A data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA\) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port.

Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These latches transfer data when the latch-enable (LE\) inputs are low. The select (SEL\) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA\, OEB\).

To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 12-bit to 24-bit bus exchanger is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors.

A data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA\) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port.

Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These latches transfer data when the latch-enable (LE\) inputs are low. The select (SEL\) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA\, OEB\).

To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74ALVCH16271 数据表 (Rev. G) 2004-8-16
应用手册 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018-9-17

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封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 56 Ultra Librarian
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