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SN74ALVCH16240

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具有总线保持和三态输出的 16 通道、1.65V 至 3.6V 反相器

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数据表

SN74ALVCH16240

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产品详情

Technology family ALVC Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ALVC Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm)
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs and symmetrical active-low output-enable (OE\) inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16240 is characterized for operation from -40°C to 85°C.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs and symmetrical active-low output-enable (OE\) inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16240 is characterized for operation from -40°C to 85°C.
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SN74LVTH16240 正在供货 具有总线保持、TTL 兼容型 CMOS 输入和三态输出的 16 通道、2.7V 至 3.6V 反相器 Voltage range 2.7V to 3.6V, average propagation delay 4.5ns, average drive strength 64mA

技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74ALVCH16240 数据表 (Rev. D) 2004-8-5
应用手册 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018-9-17

设计与开发

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仿真模型

SN74ALVCH16240 Behavioral SPICE Model

SCEM758.ZIP (7 KB) - PSpice 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 48 Ultra Librarian
SSOP (DL) 48 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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