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SN74ALVC244-EP

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具有总线保持和三态输出的增强型产品 8 通道、1.65V 至 3.6V 缓冲器

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SN74ALVC244-EP

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产品详情

Technology family ALVC Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 85
Technology family ALVC Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 85
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operates From 1.65-V to 3.6-V VCC
  • Max tpd of 2.8 ns at 3.3-V VCC
  • ±24-mA Output Drive at 3.3-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operates From 1.65-V to 3.6-V VCC
  • Max tpd of 2.8 ns at 3.3-V VCC
  • ±24-mA Output Drive at 3.3-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74ALVC244-EP 数据表 (Rev. A) 2004-9-29
* 辐射与可靠性报告 SN74ALVC244IPWREP Reliability Report 2012-3-15
* VID SN74ALVC244-EP VID V6204762 2016-6-21

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封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (PW) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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