SN74ALVC162836

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具有三态输出的 20 位通用总线驱动器

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数据表

document-pdfAcrobat SN74ALVC162836 数据表 (Rev. E) (英语)

SN74ALVC162836

正在供货

数据表

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产品详情

Number of channels

20

IOL (max) (mA)

12

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

20

IOL (max) (mA)

12

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² (18.42 mm × 10.35 mm)

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

TVSOP (DGV)

56

72.32 mm² (11.3 mm × 6.4 mm)

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Max t_pd of 4 ns at 3.3 V
±12-mA Output Drive at 3.3 V
Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments Incorporated.

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Max t_pd of 4 ns at 3.3 V
±12-mA Output Drive at 3.3 V
Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments Incorporated.

This 20-bit universal bus driver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 20-bit universal bus driver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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