SN74ALVC126

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具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器

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数据表

document-pdfAcrobat SN74ALVC126 数据表 (Rev. J) (英语)

SN74ALVC126

正在供货

立即订购

产品详情

Technology family

ALVC

Number of channels

4

IOL (max) (mA)

24

Supply current (max) (µA)

10

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ALVC

Number of channels

4

IOL (max) (mA)

24

Supply current (max) (µA)

10

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

TVSOP (DGV)

14

23.04 mm² (3.6 mm × 6.4 mm)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.1 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.1 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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