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SN74ALS112A

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具有清零和预置端的双路下降沿触发式 J-K 触发器

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SN74ALS112A

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产品详情

Number of channels 2 Technology family ALS Input type TTL Output type Push-Pull Clock frequency (MHz) 34 Supply current (max) (µA) 4000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Clear, High speed (tpd 10-50ns), Negative edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Technology family ALS Input type TTL Output type Push-Pull Clock frequency (MHz) 34 Supply current (max) (µA) 4000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Clear, High speed (tpd 10-50ns), Negative edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 
  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.

 

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.

 
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 数据表 (Rev. A) 1994-12-1

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