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SN74AHCT240-Q1

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具有 TTL 兼容型 CMOS 输入的汽车类 8 通道、4.5V 至 5.5V 反相器

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SN74AHCT240-Q1

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产品详情

Technology family AHCT Number of channels 8 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Automotive Operating temperature range (°C) -40 to 85
Technology family AHCT Number of channels 8 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Automotive Operating temperature range (°C) -40 to 85
VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm) VQFN (RKS) 20 11.25 mm² (4.5 mm × 2.5 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Qualified for Automotive Applications
  • Inputs Are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Qualified for Automotive Applications
  • Inputs Are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AHCT240 device is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AHCT240 device is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Octal Buffer/Driver With 3-State Outputs 数据表 (Rev. B) 2008-4-24
更多文献资料 汽车逻辑器件 英语版 2014-2-5

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评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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仿真模型

SN74AHCT240 Behavioral SPICE Model

SLCM006.ZIP (7 KB) - PSpice 模型
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封装 引脚 CAD 符号、封装和 3D 模型
VSSOP (DGS) 20 Ultra Librarian
VQFN (RKS) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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