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D 型触发器

SN74ACT74-EP

不推荐用于新设计

具有清零和预置端的增强型产品双路正边沿触发式 D 型触发器

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SN74ACT74-EP

不推荐用于新设计
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产品详情

Number of channels 2 Technology family ACT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Number of channels 2 Technology family ACT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm)
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74ACT74-EP 数据表 2003-9-30
* 辐射与可靠性报告 SN74ACT74MDREP Reliability Report 2012-6-4
* VID SN74ACT74-EP VID V6204725 2016-6-21

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