主页 逻辑和电压转换 缓冲器、驱动器和收发器 反向缓冲器和驱动器
主页
逻辑和电压转换
缓冲器、驱动器和收发器
反向缓冲器和驱动器

SN74ACT16373-EP

正在供货

具有施密特触发输入的增强型产品 16 通道、4.5V 至 5.5V 反相器

立即订购
数据表

SN74ACT16373-EP

正在供货
数据表 立即订购

产品详情

Technology family ACT Number of channels 16 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 160 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
Technology family ACT Number of channels 16 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 160 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm)
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Member of the Texas Instruments Widebus™ Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Bus Driving True Outputs
  • Full Parallel Access for Loading
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise

Widebus is a trademark of Texas Instruments.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Member of the Texas Instruments Widebus™ Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Bus Driving True Outputs
  • Full Parallel Access for Loading
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise

Widebus is a trademark of Texas Instruments.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.

The SN74ACT16373Q-EP is a 16-bit D-type transparent latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system, without need for interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74ACT16373Q-EP is a 16-bit D-type transparent latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system, without need for interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
filter 查找其他 反向缓冲器和驱动器
下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 3
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 16-Bit D-Type Transparent Latch With 3-State Outputs 数据表 (Rev. B) 2002-7-30
* VID SN74ACT16373-EP VID V6203602 2016-6-21
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

封装 引脚 CAD 符号、封装和 3D 模型
SSOP (DL) 48 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

视频