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D 型锁存器

SN54LVC373A

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具有三态输出的八路透明 D 型锁存器

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SN54LVC373A

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产品详情

Number of channels 8 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 20 79.0321 mm² (— mm × — mm) CFP (W) 20 90.5828 mm² (— mm × — mm) CDIP (J) 20 167.464 mm² (— mm × — mm)
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation
    on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • On Products Compliant to MIL-PRF-38535, All
    Parameters Are Tested Unless Otherwise Noted.
    On All Other Products, Production Processing
    Does Not Necessarily Include Testing of All
    Parameters.
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation
    on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • On Products Compliant to MIL-PRF-38535, All
    Parameters Are Tested Unless Otherwise Noted.
    On All Other Products, Production Processing
    Does Not Necessarily Include Testing of All
    Parameters.

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

For all available packages, see the orderable addendum at the end of the data sheet.

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

For all available packages, see the orderable addendum at the end of the data sheet.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs 数据表 (Rev. T) PDF | HTML 2013-11-21
* SMD SN54LVC373A SMD 5962-97573 2016-6-21
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15

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封装 引脚 CAD 符号、封装和 3D 模型
LCCC (FK) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
CDIP (J) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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