主页 开关与多路复用器 数字多路信号分离器和解码器
主页
开关与多路复用器
数字多路信号分离器和解码器

SN54LVC138A

正在供货

3 线至 8 线解码器/多路信号分离器

立即订购
数据表

SN54LVC138A

正在供货
立即订购

产品详情

Technology family LVC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 10
Technology family LVC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 10
CFP (W) 16 69.319 mm² (— mm × — mm) CDIP (J) 16 135.3552 mm² (— mm × — mm) LCCC (FK) 20 79.0321 mm² (— mm × — mm)
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
filter 查找其他 数字多路信号分离器和解码器
下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 2
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74LVC138A 3-Line to 8-Line Decoders Demultiplexers 数据表 (Rev. W) PDF | HTML 2016-11-11
* SMD SN54LVC138A SMD 5962-97526 2016-6-21

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

封装 引脚 CAD 符号、封装和 3D 模型
CFP (W) 16 Ultra Librarian
CDIP (J) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

视频