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SN54AS821A

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具有三态输出的 10 位总线接口触发器

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SN54AS821A

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产品详情

Number of channels 10 Technology family AS Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 125 IOL (max) (mA) 48 IOH (max) (mA) -24 Supply current (max) (µA) 113000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 10 Technology family AS Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 125 IOL (max) (mA) 48 IOH (max) (mA) -24 Supply current (max) (µA) 113000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (JT) 24 221.44 mm² (— mm × — mm)
  • Functionally Equivalent to AMD's AM29821
  • Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
  • Outputs Have Undershoot-Protection Circuitry
  • Power-Up High-Impedance State
  • Buffered Control Inputs to Reduce
    dc Loading Effects
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 
  • Functionally Equivalent to AMD's AM29821
  • Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
  • Outputs Have Undershoot-Protection Circuitry
  • Power-Up High-Impedance State
  • Buffered Control Inputs to Reduce
    dc Loading Effects
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 

These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.

A buffered output-enable () input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AS821A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS821A is characterized for operation from 0°C to 70°C.

 

 

These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.

A buffered output-enable () input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AS821A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS821A is characterized for operation from 0°C to 70°C.

 

 
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 10-Bit Bus Interface Flip-Flops With 3-State Outputs 数据表 (Rev. A) 1995-8-1
* SMD SN54AS821A SMD 5962-90780 2016-6-21

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