产品详情

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 800 Features High Performance Rating Catalog Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1750 SFDR (dB) 83 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 800 Features High Performance Rating Catalog Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1750 SFDR (dB) 83 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Dual, 16-Bit, 800 MSPS DACs
  • Dual, 16-Bit, 250 MSPS CMOS Input Data
    • 16 Sample Input FIFO
    • Flexible input data bus options
  • High Performance
    • 81 dBc ACLR WCDMA TM1 at 70 MHz
  • 2x-32x Clock Multiplying PLL/VCO
  • Selectable 2x–8x Interpolation Filters
    • Stop-band Attenuation > 80 dB
  • Complex Mixer with 32-Bit NCO
  • Digital Quadrature Modulator Correction
    • Gain, Phase and Offset Correction
  • Digital Inverse SINC Filter
  • 3- or 4-Wire Serial Control Interface
  • On Chip 1.2-V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-pin 9×9mm QFN
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

  • Dual, 16-Bit, 800 MSPS DACs
  • Dual, 16-Bit, 250 MSPS CMOS Input Data
    • 16 Sample Input FIFO
    • Flexible input data bus options
  • High Performance
    • 81 dBc ACLR WCDMA TM1 at 70 MHz
  • 2x-32x Clock Multiplying PLL/VCO
  • Selectable 2x–8x Interpolation Filters
    • Stop-band Attenuation > 80 dB
  • Complex Mixer with 32-Bit NCO
  • Digital Quadrature Modulator Correction
    • Gain, Phase and Offset Correction
  • Digital Inverse SINC Filter
  • 3- or 4-Wire Serial Control Interface
  • On Chip 1.2-V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-pin 9×9mm QFN
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference. Different modes of operation enable or bypass various signal processing blocks. The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.

The DAC5688 dual CMOS data bus provides 250 MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing. Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.

The DAC5688 allows both complex or real output. An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. A digital Inverse SINC filter compensates for natural DAC sin(x)/x frequency roll-off. The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689 which does not include a clock-multiplying PLL. The DAC5688 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference. Different modes of operation enable or bypass various signal processing blocks. The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.

The DAC5688 dual CMOS data bus provides 250 MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing. Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.

The DAC5688 allows both complex or real output. An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. A digital Inverse SINC filter compensates for natural DAC sin(x)/x frequency roll-off. The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689 which does not include a clock-multiplying PLL. The DAC5688 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 16-Bit, 800 MSPS 2x–8x Interpolating Dual-Channel Digital-to-Analog Converter (D 数据表 (Rev. C) 2010-8-19
模拟设计期刊 Q3 2009 Issue Analog Applications Journal 2018-9-24
模拟设计期刊 Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs 2009-7-14
应用手册 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009-4-28
应用手册 Passive Terminations for Current Output DACs 2008-11-10
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008-6-8
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008-6-2

设计与开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

DAC5688EVM — DAC5688 评估模块

DAC5688EVM 是一块电路板,它允许设计人员评估具有宽带 LVDS 数据输入、集成 2x/4x/8x 内插滤波器、32 位 NCO 和内部参考电压的德州仪器 (TI) 双通道 16 位 800MSPS 数模转换器 (DAC)。EVM 提供了可在各种时钟、输入条件下测试 DAC5688 的灵活环境。

它能与 TSW3100 配合使用以执行各种测试程序。TSW3100 生成了测试模式,该模式将通过单行速度可达 250MSPS 的双路 CMOS 端口被馈送至 DAC5688。DAC5688EVM 具有可使 TSW3100 板与 DAC5688 同步的可编程时钟芯片。

用户指南: PDF
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评估模块 (EVM) 用 GUI

DAC5688EVM-SW — DAC5688 EVM Software

DAC5688 EVM 软件 GUI 可对 DAC5688 进行编程控制。
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评估模块 (EVM) 用 GUI

SLLC420 — TSW3100EVM GUI v2.7

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仿真模型

DAC5688 IBIS Model (Rev. A)

SLAC178 (107 KB) - IBIS 模型
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计算工具

SLAC170 — DAC5688 LPF Calculator

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封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGC) 64 Ultra Librarian

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