DAC5681Z
- 16-Bit Digital-to-Analog Converter (DAC)
- 1.0 GSPS Update Rate
- 16-Bit Wideband Input LVDS Data Bus
- 8 Sample Input FIFO
- High Performance
- 73-dBc ACLR WCDMA TM1 at 180 MHz
- 2x to 32x Clock Multiplying PLL/VCO
- 2x or 4x Interpolation Filters
- Stopband Transition 0.4–0.6 Fdata
- Filters Configurable in Either Low-Pass or
High-Pass Mode- Allows Selection of Higher Order Image
- On-Chip 1.2-V Reference
- 2 to 20-mA Differential Scalable Output
- 64-Pin 9-mm × 9-mm VQFN Package
- APPLICATIONS
- Cellular Base Stations
- Broadband Wireless Access (BWA)
- WiMAX 802.16
- Fixed Wireless Backhaul
- Cable Modem Termination System (CMTS)
All other trademarks are the property of their respective owners
The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x to 4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.
The DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.
The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin VQFN package. Other members of the family include the dual-channel, interpolating DAC5682Z and the single-channel, non-interpolating DAC5681.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DAC. 数据表 (Rev. G) | 2015-12-3 | |||
| 应用手册 | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012-10-23 | ||||
| 用户指南 | TSW1400 Pattern Generators | 2012-5-3 | ||||
| 应用手册 | Passive Terminations for Current Output DACs | 2008-11-10 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
DAC5681ZEVM — DAC5681Z 16 位、1.0GSPS、1x-4x 插值数模转换器评估模块
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它能与 TSW3100 配合使用以执行各种测试程序。TSW3100 生成了测试模式，该模式将通过 1GSPS LVDS 接口被馈送至 DAC5681ZEVM。DAC5681ZEVM 具有可使 TSW3100 板与 DAC5681ZEVM 同步的可编程时钟芯片。
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
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