DAC5681
- 16-Bit Digital-to-Analog Converter (DAC)
- 1.0 GSPS Update Rate
- 16-Bit Wideband Input LVDS Data Bus
- 8 Sample Input FIFO
- On-Chip Delay Lock Loop
- High Performance
- 73 dBc ACLR WCDMA TM1 at 180 MHz
- On Chip 1.2 V Reference
- Differential Scalable Output: 2 to 20 mA
- Package: 64-Pin 9 × 9 mm QFN
The DAC5681 is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input and internal voltage reference. The DAC5681 offers superior linearity and noise performance.
The DAC5681 integrates a wideband LVDS port with on-chip termination, providing full 1.0 GSPS data transfer into the DAC and lower EMI than traditional CMOS data interfaces. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.
The current-steering architecture of the DAC5681 consists of a segmented array of current sinking switches directing up to 20mA of full-scale current to complementary output nodes. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.
The DAC5681 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. The device is pin upgradeable to the other members of the family: the DAC5681Z and DAC5682Z. The single-channel DAC5681Z and dual-channel DAC5682Z both provide optional 2x/4x interpolation and a clock multiplying PLL.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 16-bit 1.0 GSPS Digital-To-Analog Converter (DAC) . 数据表 (Rev. C) | 2012-8-6 | |||
| 模拟设计期刊 | Q3 2009 Issue Analog Applications Journal | 2018-9-24 | ||||
| 应用手册 | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012-10-23 | ||||
| 用户指南 | TSW1400 Pattern Generators | 2012-5-3 | ||||
| 模拟设计期刊 | Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs | 2009-7-14 | ||||
| 应用手册 | Passive Terminations for Current Output DACs | 2008-11-10 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
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