主页 逻辑和电压转换 触发器、锁存器和寄存器 D 型触发器
主页
逻辑和电压转换
触发器、锁存器和寄存器
D 型触发器

CY74FCT377T

正在供货

具有使能端的八路 D 型触发器

立即订购
数据表
用户指南

CY74FCT377T

正在供货
数据表 立即订购

产品详情

Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type CMOS, Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type CMOS, Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • Clock Enable for Address and Data Synchronization Application
  • Eight Edge-Triggered D-Type Flip-Flops
  • CY54FCT377T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT377T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • Clock Enable for Address and Data Synchronization Application
  • Eight Edge-Triggered D-Type Flip-Flops
  • CY54FCT377T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT377T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter 查找其他 D 型触发器
下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 2
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 8-Bit Registers 数据表 (Rev. A) 2001-10-1
* 用户指南 CYFCT Parameter Measurement Information 2001-4-2

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
支持的产品和硬件
有库存
限制：
??asset.out-of-stock-ti_zh_CN??
无货
封装 引脚 CAD 符号、封装和 3D 模型
SSOP (DBQ) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

视频