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CY74FCT273T

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具有清零端的八路 D 型触发器

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CY74FCT273T

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Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type CMOS, Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type CMOS, Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm)
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT273T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT273T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT273T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT273T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 8-Bit Registers 数据表 (Rev. A) 2001-10-1
* 用户指南 CYFCT Parameter Measurement Information 2001-4-2
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15

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SSOP (DBQ) 20 Ultra Librarian
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