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CY29FCT52T

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具有三态输出的八路寄存收发器

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CY29FCT52T

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Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type TTL Features Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type TTL Features Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DBQ) 24 51.9 mm² (8.65 mm × 6 mm) SOIC (DW) 24 159.65 mm² (15.5 mm × 10.3 mm)
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM2952
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM2952
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • 64-mA Output Sink Current
    32-mA Output Source Current

The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each register. Both A outputs and B outputs are specified to sink 64 mA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each register. Both A outputs and B outputs are specified to sink 64 mA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 8-Bit Registered Transceiver 数据表 (Rev. A) 2000-11-21
* 用户指南 CYFCT Parameter Measurement Information 2001-4-2

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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

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SSOP (DBQ) 24 Ultra Librarian
SOIC (DW) 24 Ultra Librarian
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