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CY29FCT520T

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8 位多级流水线寄存器

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CY29FCT520T

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Configuration Universal Bits (#) 8 Technology family FCT Input type Standard CMOS Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Configuration Universal Bits (#) 8 Technology family FCT Input type Standard CMOS Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 24 159.65 mm² (15.5 mm × 10.3 mm)
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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其他器件和数据表

该数据表适用于 CY29FCT520T 和 CY29FCT520T-MIL

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Multilevel Pipeline Register With 3-State Outputs 数据表 (Rev. C) 2001-11-2
* 用户指南 CYFCT Parameter Measurement Information 2001-4-2

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