CD74HCT574-Q1
- Qualified for Automotive Applications
- Buffered Inputs
- Common 3-State Output-Enable Control
- 3-State Outputs
- Bus-Line Driving Capability
- Typical Propagation Delay (Clock to Q):
15 ns at VCC = 5 V, CL = 15 pF, TA = 25°C - Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- VCC Voltage = 4.5 V to 5.5 V
- Direct LSTTL Input Logic Compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min)
- CMOS Input Compatibility, Il ≤ 1 µA at VOL, VOH
The CD74HCT574 is an octal D-type flip-flop with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the low-to-high transition of the clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is high, the outputs are in the high-impedance state.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | High Speed CMOS Logic Octal D-Type Flip-Flop, 3-State, Positive-Edge Triggered 数据表 (Rev. A) | 2008-4-24 | |||
| 应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022-12-15 | |||
| 更多文献资料 | 汽车逻辑器件 | 英语版 | 2014-2-5 |
设计与开发
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评估板
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (DW) | 20 | Ultra Librarian |
| TSSOP (PW) | 20 | Ultra Librarian |