CD74HC4094
- Buffered inputs
- Separate serial outputs synchronous to both positive and negative clock edges for cascading
- Fanout (over temperature range)
- Standard outputs: 10 LSTTL loads
- Bus driver outputs: 15 LSTTL loads
- Wide operating temp range: −55°C to 125°C
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL logic ICs
- HC types
- 2- to 6-V operation
- High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
- HCT types
- 4.5- to 5.5-V operation
- Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
- CMOS input compatibility, Il ≤ 1µA at VOL, VOH
The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CDx4HC4094、CD74HCT4094 三态高速 CMOS 逻辑 8 级移位和存储总线寄存器 数据表 (Rev. F) | PDF | HTML | 英语版 (Rev.F) | PDF | HTML | 2022-5-11 |
| 应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022-12-15 |
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评估板
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOT-23-THN (DYY) | 16 | Ultra Librarian |