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移位寄存器

CD54HC4094

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具有 3 级输出的高速 CMOS 逻辑 8 级移位和存储总线寄存器

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CD54HC4094

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Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² (— mm × — mm)
  • Buffered inputs
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temp range: −55°C to 125°C
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL logic ICs
  • HC types
    • 2- to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5- to 5.5-V operation
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
    • CMOS input compatibility, Il ≤ 1µA at VOL, VOH
  • Buffered inputs
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temp range: −55°C to 125°C
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL logic ICs
  • HC types
    • 2- to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5- to 5.5-V operation
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
    • CMOS input compatibility, Il ≤ 1µA at VOL, VOH

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.
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* 数据表 CDx4HC4094、CD74HCT4094 三态高速 CMOS 逻辑 8 级移位和存储总线寄存器 数据表 (Rev. F) PDF | HTML 英语版 (Rev.F) PDF | HTML 2022-5-11

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