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CD54HC4017

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具有 10 个解码输出的高速 CMOS 逻辑十进制计数器/除法器

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CD54HC4017

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Function Counter Bits (#) 10 Technology family HC Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 10 Technology family HC Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² (— mm × — mm)
  • 2-V to 6-V Operation
  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Positive-Edge Clocking
  • Balanced Propagation Delay and Transition Times
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)
  • 2-V to 6-V Operation
  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Positive-Edge Clocking
  • Balanced Propagation Delay and Transition Times
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.

The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.

The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.

The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Decade Counter/Divider With Ten Decoded Outputs 数据表 1999-3-19
* SMD CD54HC4017 SMD 8601101EA 2016-6-21

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