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Function Counter Bits (#) 4 Technology family CD4000 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Presettable, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Function Counter Bits (#) 4 Technology family CD4000 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Presettable, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • Internally synchronous for high internal and external speeds
  • Logic edge-clocked design — increments on positive Clock transition or on negative Clock inhibit transition.
  • 100% tested for quiescent current at 20-V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standard symmetrical output characteristics
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Frequency synthesizers
    • Phase-locked loops
    • Programmable down counters
    • Programmable frequency dividers

NOT RECOMMENDED FOR NEW DESIGNS

  • Internally synchronous for high internal and external speeds
  • Logic edge-clocked design — increments on positive Clock transition or on negative Clock inhibit transition.
  • 100% tested for quiescent current at 20-V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standard symmetrical output characteristics
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Frequency synthesizers
    • Phase-locked loops
    • Programmable down counters
    • Programmable frequency dividers

NOT RECOMMENDED FOR NEW DESIGNS

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.

The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.

The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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* 数据表 CD4522B TYPES 数据表 (Rev. C) 2003-10-13

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