CD4021B-Q1
- Qualified for Automotive Applications
- Medium-Speed Operation: 12-MHz (Typ) Clock Rate at VDD – VSS = 10 V
- Fully Static Operation
- Eight Master-Slave Flip-Flops Plus Output Buffering and Control Gating
- 100% Tested for Quiescent Current at 20 V
- Maximum Input Current of 1 µA at 18 V Over Full Package-Temperature Range:
100 nA at 18 V and 25°C - Noise Margin (Full Package-Temperature Range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Standardized Symmetrical Output Characteristics
- 5-V, 10-V, and 15-V Parametric Ratings
- Meets All Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of ’B’ Series CMOS Devices" - Latch-Up Performance Meets 50 mA per JESD 78, Class I
- APPLICATIONS
- Parallel Input/Serial Output Data Queuing
- Parallel-to-Serial Data Conversion
- General-Purpose Register
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CD4021B-Q1 CMOS 8-Stage Static Shift Register 数据表 | 2010-3-26 | |||
| 应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022-12-15 | |||
| 更多文献资料 | 汽车逻辑器件 | 英语版 | 2014-2-5 |
设计与开发
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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |