CD4020B
- Medium-speed operation
- Fully static operation
- Buffered inputs and outputs
- 100% tested for quiescent current at 20 V
- Standardized, symmetrical output characteristics
- Fully static operation
- Common reset
- 5-V, 10-V, and 15-V parametric ratings
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range):
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- Control counters
- Timers
- Frequency dividers
- Time-delay circuits
CD4020B - 14 Stage
CD4024B - 7 Stage
CD4040B - 12 Stage
CD4020B, CD4024B, and CD4040B are ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.
The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4040B type also is supplied in 16-lead small-outline packages (M and M96 suffixes).
The CD4024B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CD4020B, CD4024B, CD4040B TYPES 数据表 (Rev. D) | 2003-12-11 |
设计与开发
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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |