CD4017B
- Fully static operation
- Medium speed operation 10 MHz (typ.) at VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
- Applications:
- Decade counter/decimal decode display (CD4017B)
- Binary counter/decoder
- Frequency division
- Counter control/timers
- Divde-by-N counting
- For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"
CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.
These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT siganl is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes on cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CD4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.
The CD4017B and CD4022B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4017B types also are supplied in 16-lead small-outline packages (M and M96 suffixes).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CD4017B, CD4022B TYPES 数据表 (Rev. C) | 2004-2-17 |
设计与开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
PMP11112 — 6V-16V 输入的四相交错同步升压转换器音频放大器 (25V@24A) 参考设计
TIDA-00223 — 同轴 D 类放大器上汽车音频 I2S 的参考设计
该参考设计基于 I²S/TDM 技术,是一种低成本、易于使用的替代方案,可替代光纤/模拟铜线,用于连接汽车(音频)控制面板与输出级/功率放大器。它支持 I²S I和 TDM,能够将数字音频信号传输到 16 个独立的扬声器通道,每个通道在 4Ω 负载下输出功率为 80W。它还支持通过 I²C 与控制单元或处理器进行双向通信,传输介质可为单根屏蔽双绞线 (STP) 或同轴电缆。此外,TIDA-00223 参考设计包含电源模块,可实现快速部署,并满足现代汽车所需的所有保护和诊断要求。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| PDIP (N) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |