CD40106B
- Schmitt-Trigger Inputs
- Hysteresis Voltage
(Typical):
- 0.9 V at VDD = 5 V
- 2.3 V at VDD = 10 V
- 3.5 V at VDD = 15 V
- Noise Immunity Greater Than 50%
- No Limit On Input Rise and Fall Times
- Standardized, Symmetrical Output Characteristics
- For Quiescent Current at 20 V
- Maximum
Input Current Of 1 µA at 18 V Over Full Package Temperature Range:
- 100 nA at 18 V and 25°C
- Low VDD and VSS Current During Slow Input Ramp
- 5-V, 10-V, and 15-V Parametric Ratings
The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH).
The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW). All CD40106B devices are rated for –55°C to +125°C ambient temperature operation.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CD40106B CMOS Hex Schmitt-Trigger Inverters 数据表 (Rev. F) | PDF | HTML | 2017-3-9 |
设计与开发
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评估板
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| PDIP (N) | 14 | Ultra Librarian |