ADS7280
- 2.7V to 5.5V Analog Supply, Low Power:
- 13.7mW (1MHz, +VA = 3V, +VBD = 1.8V)
- 1MHz Sampling Rate 3V ≤ +VA ≤ 5.5V,
900kHz Sampling Rate 2.7V ≤ +VA ≤ 3V - Excellent DC Performance:
- ±0.4LSB Typ, ±1.0LSB Max INL
- ±0.4LSB Typ, ±1.0LSB Max DNL
- ±0.8mV Max Offset Error at 3V
- ±1.25mV Max Offset Error at 5V
- Excellent AC Performance at fi = 10kHz with 85.9dB SNR, 105.3dB SFDR, -100.1dB THD
- Built-In Conversion Clock (CCLK)
- 1.65V to 5.5V I/O Supply:
- SPI/DSP-Compatible Serial Interface
- SCLK up to 50MHz
- Comprehensive Power-Down Modes:
- Deep Power-Down
- Nap Power-Down
- Auto Nap Power-Down
- Unipolar Input Range: 0V to VREF
- Software Reset
- Global CONVST (Independent of CS)
- Programmable Status/Polarity EOC/INT
- 4 × 4 QFN-16 and TSSOP-16 Packages
- Multi-Chip Daisy-Chain Mode
- Programmable TAG Bit Output
- Auto/Manual Channel Select Mode (ADS7280)
- APPLICATIONS
- Communications
- Transducer Interface
- Medical Instruments
- Magnetometers
- Industrial Process Control
- Data Acquisition Systems
- Automatic Test Equipment
The ADS7279 is a low-power, 14-bit, 1MSPS analog-to-digital converter (ADC) with a unipolar input. The device includes a 14-bit, capacitor-based successive approximation register (SAR) ADC with inherent sample-and-hold.
The ADS7280 is based on the same core and includes a 2-to-1 input MUX with a programmable TAG bit output option. Both the ADS7279 and ADS7280 offer a high-speed, wide voltage serial interface, and are capable of daisy-chain mode operation when multiple converters are used.
These converters are available in 4 × 4 QFN and TSSOP-16 packages, and are fully specified for operation over the industrial -40°C to +85°C temperature range.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LOW-POWER, 14-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ADC w/SERIAL INTERFACE 数据表 (Rev. A) | 2009-6-17 | |||
| 电子书 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015-5-21 | ||||
| 应用手册 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011-3-17 | ||||
| 应用手册 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010-11-10 |
设计与开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算列表,从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件,以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外,该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RSA) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。