产品详情

Sample rate (max) (Msps) 105 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.7 SFDR (dB) 91 Operating temperature range (°C) -55 to 125 Input buffer No
Sample rate (max) (Msps) 105 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.7 SFDR (dB) 91 Operating temperature range (°C) -55 to 125 Input buffer No
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5-dB Coarse Gain and up to 6-dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock
    Inputs and Amplitude Down to 400 mVPP
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64-pin QFN Package (9 mm × 9 mm)
  • Feature Compatible Dual Channel Family
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5-dB Coarse Gain and up to 6-dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock
    Inputs and Amplitude Down to 400 mVPP
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64-pin QFN Package (9 mm × 9 mm)
  • Feature Compatible Dual Channel Family

The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.

The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS 数据表 (Rev. C) 2013-5-29
* VID ADS6444-EP VID V6208628 2016-6-21
* VID ADS6444-EP VID V6208628 2016-6-21

设计与开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

支持软件

HSADC-SPI-UTILITY — ADS5400 EVM GUI

支持的产品和硬件
计算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算列表,从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件,以稳定模数转换器 (ADC) 驱动器缓冲器电路。

除了可用作独立工具之外,该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。

支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGC) 64 Ultra Librarian

订购和质量

支持和培训

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