ADS6443
- Maximum Sample Rate: 125 MSPS
- 14-Bit Resolution with No Missing Codes
- Simultaneous Sample and Hold
- 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off
- Serialized LVDS Outputs with Programmable Internal Termination Option
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP
- Internal Reference with External Reference Support
- No External Decoupling Required for References
- 3.3-V Analog and Digital Supply
- 64 QFN Package (9 mm × 9 mm)
- Pin Compatible 12-Bit Family (ADS642X - SLAS532A)
- Feature Compatible Dual Channel Family (ADS624X - SLAS542A, ADS644X - SLAS543A)
- APPLICATIONS
- Base-Station IF Receivers
- Diversity Receivers
- Medical Imaging
- Test Equipment
The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS 数据表 (Rev. B) | 2009-12-16 | |||
| 应用手册 | QFN 和 SON PCB 连接 (Rev. C) | PDF | HTML | 英语版 (Rev.C) | PDF | HTML | 2024-1-5 | |
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 用户指南 | ADS6245EVM and Lattice ECP2/M Interface Demo User Guide | 2008-1-14 | ||||
| 应用手册 | QFN Layout Guidelines | 2006-7-28 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
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