ADS58C48
- Maximum Sample Rate: 200 MSPS
- High Dynamic Performance
- SFDR 82 dBc at 140 MHz
- 72.3 dBFS SNR in 60 MHz BW Using SNRBoost3G technology
- SNRBoost3G Highlights
- Supports Wide Bandwidth up to 60 MHz
- Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz
- Flat Noise Floor within the Band
- Independent SNRBoost3G Coefficients for Every Channel
- Output Interface
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100
Termination - 2x Strength: 50 Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Ultra-Low Power with Single 1.8V Supply
- 0.9W Total Power
- 1.32 W Total Power (200 MSPS) with SNRBoost3G on all 4 Channels
- 1.12 W Total Power (200 MSPS) with SNRBoost3G on 2 Channels
- Programmable Gain up to 6dB for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- 80-TQFP Package
The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS58C48 uses third-generation SNRBoost3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost3G coefficients can be programmed for each channel.
The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.
The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).
The same digital output pins can also be configured as a parallel 1.8V CMOS interface.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Quad Channel IF Receiver with SNRBoost 3G 数据表 | 2010-5-27 | |||
| 应用手册 | IC 的热特性-热阻 | 2014-1-15 | ||||
| 应用手册 | ADS58C48 切换模式在时分通信系统中的应用 | 2012-7-23 | ||||
| 应用手册 | Band-Pass Filter Design Techniques for High-Speed ADCs | 2012-2-27 | ||||
| 应用手册 | High-Speed, Analog-to-Digital Converter Basics | 2012-1-11 | ||||
| 应用手册 | Power Supply Design for the ADS41xx (Rev. A) | 2011-12-29 | ||||
| 应用手册 | Understanding Low-Amplitude Behavior of 11-bit ADCs | 2011-10-22 | ||||
| 应用手册 | SNRboost ADC | 2011-8-16 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Using Windowing With SNRBoost 3G Technology | 2010-8-30 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 |
设计与开发
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