ADS5553
- Dual ADC
- 14 Bit Resolution
- 65 MSPS Sample Rate
- High SNR = 74 dBFs at 70 MHz fIN
- High SFDR = 84 dBc at 70 MHz fIN
- 2.3 VPP Differential Input Voltage
- Internal / External Voltage Reference
- 3.3 V Single-Supply Voltage
- Analog Power Dissipation = 0.72 W
- Output Supply Power Dissipation = 0.17 W
- 80 Lead PowerPad™ TQFP Package
- Two’s Complement Output Format
- APPLICATIONS
- Communication Receivers
- Base Station Infrastructure
- Test and Measurement Instrumentation
PowerPAD and CommsADC are trademarks of Texas Instruments.
The ADS5553 is a high-performance, dual channel, 14 bit, 65 MSPS analog-to-digital converter (ADC). To provide a complete solution, each channel includes a high-bandwidth linear sample-and-hold stage (S& H) and an internal reference. Designed for applications demanding high dynamic performance in a small space, the ADS5553 has excellent power consumption of 0.9 W at 3.3 V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements, yet an external reference can be used optionally to suit the accuracy and low drift requirements of the application. The outputs are parallel CMOS compatible.
The ADS5553 is available in a 80 lead TQFP PowerPAD package and is specified over the full temperature range of -40°C to 85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Dual 14 Bit, 65 MSPS ADC 数据表 | 2005-2-21 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 模拟设计期刊 | Clocking High-Speed Data Converters | 2005-1-18 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
HSADC-SPI-UTILITY — ADS5400 EVM GUI
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面，其中显示各种常见计算列表，从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件，以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外，该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC 可用于根据输入频率和时钟抖动来计算 ADC 的理论信噪比 (SNR) 性能。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| HTQFP (PFP) | 80 | Ultra Librarian |