ADS5547
- Maximum Sample Rate: 210 MSPS
- 14-Bit Resolution
- No Missing Codes
- Total Power Dissipation 1.23 W
- Internal Sample and Hold
- 73.3-dBFS SNR at 70-MHz IF
- 85-dBc SFDR at 70-MHz IF, 0-dB gain
- High Analog Bandwidth up to 800 MHz
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
- Reduced Power Modes at Lower Sample Rates
- Supports Input Clock Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- No External Reference Decoupling Required
- Internal and External Reference Support
- Programmable Output Clock Position to Ease Data Capture
- 3.3-V Analog and Digital Supply
- 48-QFN Package (7 mm × 7 mm)
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
ADS5547 is a high performance 14-bit, 210-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. With high analog bandwidth and low jitter input clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.
In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. The ADS5547 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.
The device is specified over the industrial temperature range (-40°C to 85°C).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 14-Bit 210 MSPS ADC With DDR LVDS/CMOS Outputs 数据表 (Rev. A) | 2007-5-7 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 应用手册 | QFN Layout Guidelines | 2006-7-28 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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