ADS5424-SP
- 14-Bit Resolution
- 105-MSPS Maximum Sample Rate
- SNR = 70 dBc at 105 MSPS and 50 MHz IF
- SFDR = 78 dBc at 105 MSPS and 50 MHz IF
- 2.2-VPP Differential Input Range
- 5-V Supply Operation
- 3.3-V CMOS Compatible Outputs
- 2.3-W Total Power Dissipation
- 2s Complement Output Format
- On-Chip Input Analog Buffer, Track and Hold, and Reference Circuit
- 52-Pin Ceramic Nonconductive Tie-Bar Package (HFG)
- Military Temperature Range
( –55°C to 125°C Tcase) - QML-V Qualified, SMD 5962-07206
- Engineering Evaluation (/EM) Samples are Available(1)
- APPLICATIONS
- Single and Multichannel Digital Receivers
- Base Station Infrastructure
- Instrumentation
- Video and Imaging
- Clocking: CDC7005
- Amplifiers: OPA695, THS4509
(1) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of 55°C to 125°C or operating life.
The ADS5424 is a 14-bit, 105-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while providing 3.3-V CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the on-chip track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system design. The ADS5424 has outstanding low noise and linearity, over input frequency. With only a 2.2-VPP input range, ADS5424 simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5424 is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The ADS5424 is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full military temperature range (–55°C to 125°C Tcase)
This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends a 16-mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically at ground potential.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Class V, 14 Bit, 105 MSPS Analog-to-Digital Converter 数据表 (Rev. D) | 2013-9-16 | |||
| * | 辐射与可靠性报告 | ADS5424-SP Radiation Report | 2016-12-5 | |||
| * | 辐射与可靠性报告 | ADS5424 SEE Report | 2015-3-26 | |||
| * | SMD | ADS5424-SP SMD 5962-07206 | 2016-7-8 | |||
| 选择指南 | TI Space Products (Rev. L) | 2026-3-27 | ||||
| 应用简报 | 经 DLA 批准的 QML 产品优化 (Rev. C) | PDF | HTML | 英语版 (Rev.C) | PDF | HTML | 2025-8-18 | |
| 应用手册 | 重离子轨道环境单粒子效应估算 (Rev. B) | PDF | HTML | 英语版 (Rev.B) | PDF | HTML | 2025-7-7 | |
| 更多文献资料 | TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) | 2025-2-20 | ||||
| 应用手册 | 单粒子效应置信区间计算 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | PDF | HTML | 2022-12-2 | |
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 |
设计与开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算列表,从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件,以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外,该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| CFP (HFG) | 52 | Ultra Librarian |