ADS1602
- High Speed:
- Data Rate: 2.5MSPS
- Bandwidth: 1.23MHz
- Outstanding Performance:
- SNR: 91dB at fIN = 100kHz, –1dBFS
- THD: –101dB at fIN = 100kHz, –6dBFS
- SFDR: 103dB at fIN = 100kHz, –6dBFS
- Ease-of-Use:
- High-Speed 3-Wire Serial Interface
- Directly Connects to TMS320 DSPs
- On-Chip Digital Filter Simplifies Antialias Requirements
- Simple Pin-Driven Control—No On-Chip Registers to Program
- Selectable On-Chip Voltage Reference
- Simultaneous Sampling with Multiple ADS1602s
- Low Power:
- 530mW at 2.5MSPS
- Power-Down Mode
The ADS1602 is a high-speed, high-precision, delta-sigma (ΔΣ) analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1602 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs. Consequently, signal-to-noise ratio (SNR) is particularly improved. Total harmonic distortion (THD) is –101dB, and the spurious-free dynamic range (SFDR) is 103dB.
Optimized for power and performance, the ADS1602 dissipates only 530mW while providing a full-scale differential input range of ±3V. Having such a wide input range makes out-of-range signals unlikely. The OTR pin indicates if an analog input out-of-range condition does occur. The differential input signal is measured against the differential reference, which can be generated internally or supplied externally on the ADS1602.
The ADS1602 uses an inherently stable advanced modulator with an on-chip decimation filter. The filter stop band extends to 38.6MHz, which greatly simplifies the antialiasing circuitry. The modulator samples the input signal up to 40MSPS, depending on fCLK, while the 16x decimation filter uses a series of four half-band FIR filter stages to provide 75dB of stop band attenuation and 0.001dB of passband ripple.
Output data is provided over a simple 3-wire serial interface at rates up to 2.5MSPS, with a –3dB bandwidth of 1.23MHz. The output data or its complementary format directly connects to DSPs such as TI’s TMS320 family, FPGAs, or ASICs. A dedicated synchronization pin enables simultaneous sampling with multiple ADS1602s in multi-channel systems. Power dissipation is set by an external resistor that allows a reduction in dissipation when operating at slower speeds. All of the ADS1602 features are controlled by dedicated I/O pins, which simplify operation by eliminating the need for on-chip registers.
The high performing, easy-to-use ADS1602 is especially suitable for demanding measurement applications in sonar, vibration analysis, and data acquisition. The ADS1602 is offered in a small, 7mm × 7mm TQFP-48 package and is specified from –40°C to +85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 16-Bit, 2.5MSPS Analog-to-Digital Converter 数据表 (Rev. E) | 2011-10-20 | |||
| 应用手册 | Δ-Σ ADC 中的数字滤波器类型 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | PDF | HTML | 2023-4-13 | |
| 应用手册 | ADS16axx 基准选项 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | PDF | HTML | 2022-8-23 | |
| 电子书 | Fundamentals of Precision ADC Noise Analysis (Rev. A) | 2020-6-19 | ||||
| 白皮书 | Voltage-reference impact on total harmonic distortion | 2016-8-1 | ||||
| 电子书 | Best of Baker's Best: Precision Data Converters -- Delta-Sigma ADCs | 2015-3-19 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面，其中显示各种常见计算列表，从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件，以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外，该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。