ADC16DV160
- Low Power Consumption
- On-Chip Precision Reference and Sample-and-Hold Circuit
- On-Chip Automatic Calibration During Power-Up
- Dual Data Rate LVDS Output Port
- Dual Supplies: 1.8V and 3.0V Operation
- Selectable Input Range: 2.4 and 2.0 VPP
- Sampling Edge Flipping with Clock Divider by 2 Option
- Internal Clock Divide by 1 or 2
- On-Chip Low Jitter Duty-Cycle Stabilizer
- Power-Down and Sleep Modes
- Output Fixed Pattern Generation
- Output Clock Position Adjustment
- 3-Wire SPI
- Offset Binary or 2's Complement Data Format
- 68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)
Key Specifications
- Resolution: 16 Bits
- Conversion Rate: 160 MSPS
- SNR (@FIN = 30 MHz): 78 dBFS (typ)
- SNR (@FIN = 197 MHz): 76 dBFS (typ)
- SFDR (@FIN = 30 MHz): 95 dBFS (typ)
- SFDR (@FIN = 197 MHz): 89 dBFS (typ)
- Full Power Bandwidth: 1.4 GHz (typ)
- Power
Consumption:
- Core per channel: 612 mW (typ)
- LVDS Driver: 117 mW (typ)
- Total: 1.3W (typ)
- Operating Temperature Range (-40°C ~ 85°C)
The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs 数据表 (Rev. H) | 2013-2-19 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Signal Chain Noise Figure Analysis | 2014-10-29 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) | 2013-4-26 | ||||
| 应用手册 | Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) | 2013-4-26 | ||||
| 应用手册 | Between the Amplifier and ADC: Managing Filter Loss in Communications Systems (Rev. B) | 2013-4-26 | ||||
| 用户指南 | High-IF Sub-sampling Receiver Subsystem User Guide | 2012-1-27 |
设计与开发
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WAVEVISION5 — WaveVision 5 Software
WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.
While WaveVision 5 software (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFNP (NKE) | 68 | Ultra Librarian |
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