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模数转换器 (ADC)
高速 ADC (≥10 MSPS)

ADC12QS065

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四通道、12 位、65MSPS 模数转换器 (ADC)

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ADC12QS065

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产品详情

Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 300 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 828 Architecture Pipeline SNR (dB) 69.3 ENOB (Bits) 11.2 SFDR (dB) 83.3 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 300 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 828 Architecture Pipeline SNR (dB) 69.3 ENOB (Bits) 11.2 SFDR (dB) 83.3 Operating temperature range (°C) -40 to 85 Input buffer No
WQFN (NKA) 60 81 mm² (9 mm × 9 mm)
  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold and Internal Reference
  • Low Power Consumption
  • Power Down Mode
  • Clock and Data Frame Timing
  • 780 Mbps Serial LVDS Data Rate (at 65 MHz Clock)
  • LVDS Serial Output Rated for 100 Ohm Load

Key Specifications

  • Resolution: 12 Bits
  • DNL: ±0.3 LSB (Typ)
  • SNR (fIN = 5 MHz): 69 dB (Typ)
  • SFDR (fIN = 5 MHz): 83 dB (Typ)
  • ENOB (at Nyquist): 11 Bits (Typ)
  • Power Consumption
    • Operating, 65 MSPS, per ADC: 200 mW (Typ)
    • Power Down Mode: < 3 mW (Typ)

All trademarks are the property of their respective owners.

  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold and Internal Reference
  • Low Power Consumption
  • Power Down Mode
  • Clock and Data Frame Timing
  • 780 Mbps Serial LVDS Data Rate (at 65 MHz Clock)
  • LVDS Serial Output Rated for 100 Ohm Load

Key Specifications

  • Resolution: 12 Bits
  • DNL: ±0.3 LSB (Typ)
  • SNR (fIN = 5 MHz): 69 dB (Typ)
  • SFDR (fIN = 5 MHz): 83 dB (Typ)
  • ENOB (at Nyquist): 11 Bits (Typ)
  • Power Consumption
    • Operating, 65 MSPS, per ADC: 200 mW (Typ)
    • Power Down Mode: < 3 mW (Typ)

All trademarks are the property of their respective owners.

The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.3V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost.

No missing codes performance is ensured over the full operating temperature range. The pipeline ADC architecture achieves 11 Effective Bits over the entire Nyquist band at 65 MSPS.

When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less than 5 ms. The ADC12QS065's speed, resolution and single supply operation makes it well suited for a variety of applications in ultrasound, imaging, video and communications. Operating over the industrial (-40°C to +85°C) temperature range, the ADC12QS065 is available in a 60-pin WQFN package with exposed pad (9x9x0.8mm, 0.5mm pin pitch).

The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.3V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost.

No missing codes performance is ensured over the full operating temperature range. The pipeline ADC architecture achieves 11 Effective Bits over the entire Nyquist band at 65 MSPS.

When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less than 5 ms. The ADC12QS065's speed, resolution and single supply operation makes it well suited for a variety of applications in ultrasound, imaging, video and communications. Operating over the industrial (-40°C to +85°C) temperature range, the ADC12QS065 is available in a 60-pin WQFN package with exposed pad (9x9x0.8mm, 0.5mm pin pitch).

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs 数据表 (Rev. I) 2013-4-12
应用手册 Understanding High-Speed Signals, Clocks, and Data Capture 2005-10-18
白皮书 Data Converter Serial LVDS Interface Improves Board Routing 2005-8-1

设计与开发

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仿真模型

ADC12QS065 IBIS Model

SNOM006.ZIP (5 KB) - IBIS 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
WQFN (NKA) 60 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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