产品详情

Sample rate (max) (Msps) 3000 Resolution (Bits) 8 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 3000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.82 Power consumption (typ) (mW) 1900 Architecture Folding Interpolating SNR (dB) 45.4 ENOB (Bits) 7.2 SFDR (dB) 57 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3000 Resolution (Bits) 8 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 3000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.82 Power consumption (typ) (mW) 1900 Architecture Folding Interpolating SNR (dB) 45.4 ENOB (Bits) 7.2 SFDR (dB) 57 Operating temperature range (°C) -40 to 85 Input buffer Yes
HLQFP (NNB) 128 484 mm² (22 mm × 22 mm)

  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR output clocking
  • Serial Interface for Extended Control
  • Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock
  • Test pattern

  • Key Specifications

    Resolution

    8 Bits

    Max Conversion Rate

    3 GSPS (min)

    Error Rate

    10 -18 (typ)

    ENOB @ 748 MHz Input

    7.0 Bits (typ)

    SNR @ 748 MHz

    44.5 dB (typ)

    Full Power Bandwidth

    3 GHz (typ)

  • Power Consumption
  • Operating

    1.9 W (typ)

    Power Down Mode

    25 mW (typ)


  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR output clocking
  • Serial Interface for Extended Control
  • Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock
  • Test pattern

  • Key Specifications

    Resolution

    8 Bits

    Max Conversion Rate

    3 GSPS (min)

    Error Rate

    10 -18 (typ)

    ENOB @ 748 MHz Input

    7.0 Bits (typ)

    SNR @ 748 MHz

    44.5 dB (typ)

    Full Power Bandwidth

    3 GHz (typ)

  • Power Consumption
  • Operating

    1.9 W (typ)

    Power Down Mode

    25 mW (typ)


    The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.9 Watts at 3 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10 -18 Word Error Rate. The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.5 GHz input clock. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.15V.

    The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate.

    The converter typically consumes less than 25 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C TA +85°C) temperature range.


    The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.9 Watts at 3 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10 -18 Word Error Rate. The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.5 GHz input clock. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.15V.

    The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate.

    The converter typically consumes less than 25 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C TA +85°C) temperature range.


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    技术文档

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    顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
    * 数据表 ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter 数据表 (Rev. N) 2009-7-6
    技术文章 RF sampling: aliasing can be your friend PDF | HTML 2015-7-22
    用户指南 Single low power, ultra high speed CMOS A/D Converter User Guide 2012-1-27
    应用手册 Selecting Amplifiers, ADCs, and Clocks for High-Performance Signal Paths 2007-9-13

    设计与开发

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    仿真模型

    ADC083000 IBIS Model

    SNAM005.ZIP (9 KB) - IBIS 模型
    支持的产品和硬件
    封装 引脚 CAD 符号、封装和 3D 模型
    HLQFP (NNB) 128 Ultra Librarian

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